FPGA IP Design and Verification Engineer

Company

Altera

Where

Regus, Madhapur

Level

Mid

First seen

September 22, 2026

Listed via

Workday

What the posting says

Job Description: Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL…

Read more and apply on Altera's site

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