CPU Design Verification Engineer II
SiFive is hiring for CPU Design Verification Engineer II in Hyderabad, India. Mid level. First seen November 3, 2026; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- SiFive
- Where
- Hyderabad, India
- Level
- Mid
- First seen
- November 3, 2026
- Listed via
- Workday
What the posting says
This is a hands-on role at the block and core level: you'll write testbench components, build constrained-random and directed stimulus, close coverage, and debug the hard failures that come out of nightly regressions — pipeline hazards, memory-ordering violations, speculation and flush corner cases, and co-simulation divergences between RTL and the golden ISA model. You'll work directly with core micro-architects and RTL designers, and you'll own verification of specific units (e.g. rename/dispatch, issue queues, load-store unit, MMU/TLB, branch prediction, or the retire/commit path) as well…
Read more and apply on SiFive's site
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