Destava

HPC SoC Timing Design Engineer/Leader

Hop is hiring for HPC SoC Timing Design Engineer/Leader in Japan. Senior level. First seen August 6, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.

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Company
Hop
Where
Japan
Level
Senior
First seen
August 6, 2026
Listed via
Lever

What the posting says

From a timing design perspective, efficient development of large-scale, complex SoC products with short turnaround times is essential, and we are seeking engineers/leaders who can develop products innovatively. Furthermore, since design is carried out in collaboration with design centers in Vietnam and India (language: English), we are looking for engineers who can thrive globally. Responsibilities Design Engineer or Design Leader for SoC Timing Design (STA, SDC, Synthesis). Timing design (static timing analysis, timing constraint analysis, logic synthesis technology development, product…

Read more and apply on Hop's site

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