Staff DV Engineer
E-Space is hiring for Staff DV Engineer in Saratoga, CA. Staff level. First seen August 6, 2026; open as of November 10, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- E-Space
- Where
- Saratoga, CA
- Level
- Staff
- First seen
- August 6, 2026
- Listed via
- Lever
What the posting says
We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work. Requirements HDL & Verification Methodology · Strong proficiency in Verilog and SystemVerilog · Experience writing tests within an existing UVM verification environment · Solid understanding of UVM architecture and methodology Programming & Scripting · Ability to write C/C++ code for verification purposes · Some scripting experience in Perl or Python…
Read more and apply on E-Space's site
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