Layout Scale-Up Engineer
Alice & Bob is hiring for Layout Scale-Up Engineer in Paris. Senior level. First seen September 17, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.
With Destava: How well do you fit? · Tailor my résumé · Write a cover letter
- Company
- Alice & Bob
- Where
- Paris
- Level
- Senior
- First seen
- September 17, 2026
- Listed via
- Lever
What the posting says
This role exists to build the infrastructure — PDK, generators, automated flows — that lets chip complexity grow 10–1,000× while design cycle time stays flat. About the Role You'll build the layout infrastructure that makes that scaling possible — PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation. This is a semiconductor physical-design role applied to superconducting hardware, not a quantum physics one. Responsibilities Build and own the PDK — layer stack, technology file, parametric cells (junctions, CPW, resonators, couplers, pads,…
Read more and apply on Alice & Bob's site
More jobs like this
A search agent finds the jobs this list misses: the ones that mean the same without the same words. Have Destava watch for layout scale-up engineer jobs in Paris, new matches every morning on your own account.
This page includes information from the O*NET 31.0 Database by the U.S. Department of Labor, Employment and Training Administration (USDOL/ETA). Used under the CC BY 4.0 license. O*NET® is a trademark of USDOL/ETA.