DFT (Design For Test) Engineer
Etched is hiring for DFT (Design For Test) Engineer in San Jose. Senior level. First seen August 6, 2026, posted 2 times; open as of November 8, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Etched
- Where
- San Jose
- Level
- Senior
- First seen
- August 6, 2026
- Postings
- 2
- Listed via
- Ashby
What the posting says
The ideal candidate will be responsible for ensuring the robust testability of integrated circuits (ICs) from the design phase through to production. This role is crucial in improving the efficiency and effectiveness of our testing processes, thereby enhancing overall product quality. Key responsibilities - Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation. - Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST…
Read more and apply on Etched's site
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