Formal Verification - DV
Etched is hiring for Formal Verification - DV in San Jose. Mid level. First seen August 6, 2026, posted 2 times; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
With Destava: How well do you fit? · Tailor my résumé · Write a cover letter
- Company
- Etched
- Where
- San Jose
- Level
- Mid
- First seen
- August 6, 2026
- Postings
- 2
- Listed via
- Ashby
What the posting says
You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip. Key Responsibilities - Define and drive formal verification strategy across the ASIC DV team for complex IP blocks,…
Read more and apply on Etched's site
More jobs like this
A search agent finds the jobs this list misses: the ones that mean the same without the same words. Have Destava watch for formal verification - dv jobs in San Jose, new matches every morning on your own account.
This page includes information from the O*NET 31.0 Database by the U.S. Department of Labor, Employment and Training Administration (USDOL/ETA). Used under the CC BY 4.0 license. O*NET® is a trademark of USDOL/ETA.