Staff Analog Design Engineer, SerDes Clocking
d-Matrix is hiring for Staff Analog Design Engineer, SerDes Clocking in Santa Clara. Staff level. First seen November 7, 2026, posted 2 times; open as of November 8, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- d-Matrix
- Where
- Santa Clara
- Level
- Staff
- First seen
- November 7, 2026
- Postings
- 2
- Listed via
- Ashby
What the posting says
ROLE OVERVIEW This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization. The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and…
Read more and apply on d-Matrix's site
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