Senior or Staff Design Verification Engineer
Powerlattice Technologies is hiring for Senior or Staff Design Verification Engineer in HQ - Vancouver, WA. Senior level, $160k–$190k a year stated. First seen November 7, 2026, posted 2 times; open as of November 10, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Powerlattice Technologies
- Where
- HQ - Vancouver, WA
- Level
- Senior
- Pay stated
- $160k–$190k a year
- First seen
- November 7, 2026
- Postings
- 2
- Listed via
- Ashby
What the posting says
This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues. Key Responsibilities - Lead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies, test scenarios, coverage goals, and signoff criteria. - Architect, develop, and maintain SystemVerilog-based verification environments and reusable…
Read more and apply on Powerlattice Technologies' site
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