Power Optimization Engineer
Etched is hiring for Power Optimization Engineer in Cupertino, CA. Mid level. First seen August 6, 2026; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Etched
- Where
- Cupertino, CA
- Level
- Mid
- First seen
- August 6, 2026
- Listed via
- Greenhouse
What the posting says
Key responsibilities Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases. Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques. Estiate and analyze power consumption data at both full-chip and unit levels, guiding ASIC teams to enhance the power efficiency of all functional units both pre-silicon and post silicon. Correlate the estimated power…
Read more and apply on Etched's site
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