PCIe ASIC Design Engineer
Cornelis Networks is hiring for PCIe ASIC Design Engineer in Not specified. Mid level. First seen September 3, 2026; open as of November 6, 2026. Jobs taken straight from company career pages — no aggregator in between.
With Destava: How well do you fit? · Tailor my résumé · Write a cover letter
- Company
- Cornelis Networks
- Where
- Not specified
- Level
- Mid
- First seen
- September 3, 2026
- Listed via
- BambooHR
What the posting says
The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6), integration into high performance ASICs, emulation and post silicon bring-up. Key Responsibilities: - Own end-to-end integration of PCIe IP into complex ASIC designs. - Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems. - Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency. - Contribute to system architecture and microarchitecture discussions with a focus on IO and…
Read more and apply on Cornelis Networks' site
More jobs like this
A search agent finds the jobs this list misses: the ones that mean the same without the same words. Have Destava watch for pcie asic design engineer jobs in Not specified, new matches every morning on your own account.