ASIC Power Design Engineer II (Full Time) - United States
Cisco Systems is hiring for ASIC Power Design Engineer II (Full Time) - United States in San Jose, California, US. Mid level, $126k–$203k a year stated. First seen November 4, 2026; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Cisco Systems
- Where
- San Jose, California, US
- Level
- Mid
- Pay stated
- $126k–$203k a year
- First seen
- November 4, 2026
- Listed via
- Workday
What the posting says
Minimum Qualifications - Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience. (Relevant fields include ASIC Design or Power Design.) - Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, leakage vs. dynamic power trade-offs). - Proficiency with hardware description languages (SystemVerilog / Verilog). - Scripting capability in TCL, Python,…
Read more and apply on Cisco Systems' site
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