Destava

ASIC Physical Design Technical Lead

Cisco Systems is hiring for ASIC Physical Design Technical Lead in San Jose, California, US. Senior level, $187k–$268k a year stated. First seen November 4, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.

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Company
Cisco Systems
Where
San Jose, California, US, Austin, Texas, US
Level
Senior
Pay stated
$187k–$268k a year
First seen
November 4, 2026
Listed via
Workday

What the posting says

Your Impact - Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints - Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan - Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods - RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and…

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