Destava

ASIC Design Technical Lead (CPU subsystems)

Cisco Systems is hiring for ASIC Design Technical Lead (CPU subsystems) in San Jose, California, US. Senior level, $187k–$268k a year stated. First seen November 10, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.

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Company
Cisco Systems
Where
San Jose, California, US
Level
Senior
Pay stated
$187k–$268k a year
First seen
November 10, 2026
Listed via
Workday

What the posting says

We are seeking a highly experienced designer to lead the architecture and design of complex CPU subsystems for our next-generation high-performance networking switch ASICs. You will use your expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up. You will collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models, while supporting early emulation and FPGA platforms. Minimum Qualifications: - Bachelor’s + 8 years of related…

Read more and apply on Cisco Systems' site

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