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ASIC DFT STA Engineer

Cisco Systems is hiring for ASIC DFT STA Engineer in San Jose, California, US. Mid level. First seen October 23, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.

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Company
Cisco Systems
Where
San Jose, California, US
Level
Mid
First seen
October 23, 2026
Listed via
Workday

What the posting says

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases…

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