ASIC DFT Engineer - Acacia (Hybrid)
Cisco Systems is hiring for ASIC DFT Engineer - Acacia (Hybrid) in San Jose, California, US. Mid level. First seen October 28, 2026; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Cisco Systems
- Where
- San Jose, California, US
- Level
- Mid
- First seen
- October 28, 2026
- Listed via
- Workday
What the posting says
Your Impact We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include: - Support DFT…
Read more and apply on Cisco Systems' site
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