ASIC Engineer | RTL Design, Verilog, System Verilog | CDC, Lint | Exp - 8 to 10 years | Bangalore
Cisco Systems is hiring for ASIC Engineer | RTL Design, Verilog, System Verilog | CDC, Lint | Exp - 8 to 10 years | Bangalore in Bangalore, India. Senior level. First seen November 12, 2026; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Cisco Systems
- Where
- Bangalore, India
- Level
- Senior
- First seen
- November 12, 2026
- Listed via
- Workday
What the posting says
Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Technical Leader. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. - Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. - All aspects of implementation: specification, design, timing-analysis,…
Read more and apply on Cisco Systems' site
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