ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years
Cisco Systems is hiring for ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years in Bangalore, India. Senior level. First seen October 20, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Cisco Systems
- Where
- Bangalore, India
- Level
- Senior
- First seen
- October 20, 2026
- Listed via
- Workday
What the posting says
You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact : As a Design Verification Engineer specializing in Simulation, you will be responsible for developing and executing verification strategies to ensure the correctness and performance of complex hardware designs. Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage. Key Responsibilities: - Develop and implement verification plans…
Read more and apply on Cisco Systems' site
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