Destava

Senior Principal Digital Design Engineer - Memory IP

CADENCE US is hiring for Senior Principal Digital Design Engineer - Memory IP in SAN JOSE. Staff level, $154k–$286k a year stated. First seen November 3, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.

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Company
CADENCE US
Where
SAN JOSE
Level
Staff
Pay stated
$154k–$286k a year
First seen
November 3, 2026
Listed via
Workday

What the posting says

Position Overview As a Senior Principal Digital Design Engineer, you will be responsible for the design, development, and ongoing support of system-level memory IP models used in hardware-based verification products. You will work across a broad range of memory technologies and interfaces, including SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS. In addition to developing new memory models, you will maintain and enhance existing products to ensure performance, quality, usability, and long-term customer support. This role is a highly collaborative…

Read more and apply on CADENCE US' site

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