Memory Layout Design Engineer
broadcom is hiring for Memory Layout Design Engineer in IND-Bangalore Electronic City - S1. Senior level. First seen August 8, 2026, posted 5 times; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.
With Destava: How well do you fit? · Tailor my résumé · Write a cover letter
- Company
- broadcom
- Where
- IND-Bangalore Electronic City - S1
- Level
- Senior
- First seen
- August 8, 2026
- Postings
- 5
- Listed via
- Workday
What the posting says
Job Description: Job Requirements: - Minimum 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree, strong layout knowledge. - Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules). - Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes. Key Responsibilities: - Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts. - Manage scheduling,…
Read more and apply on broadcom's site
More jobs like this
Signal and Power Integrity Technical Leader | 8 to 15 years | Bangalore
Save to applySenior Staff Hardware Engineer
Save to applyBackend Physical Design Engineer
Save to applyASIC Engineer || 2028822 ASIC Engineer || Design Verification, UVM, Testbench || Exp- 8+ years
Save to apply
See all 94 Computer Hardware Engineers jobs in Bangalore
A search agent finds the jobs this list misses: the ones that mean the same without the same words. Have Destava watch for memory layout design engineer jobs in IND-Bangalore Electronic City - S1, new matches every morning on your own account.
This page includes information from the O*NET 31.0 Database by the U.S. Department of Labor, Employment and Training Administration (USDOL/ETA). Used under the CC BY 4.0 license. O*NET® is a trademark of USDOL/ETA.