Destava

Senior FPGA IP Design Engineer

Altera is hiring for Senior FPGA IP Design Engineer in Bengaluru, Karnataka, India. Senior level. First seen October 21, 2026; open as of November 12, 2026. Jobs taken straight from company career pages — no aggregator in between.

Save to applyRead more and apply on Altera's site

With Destava: How well do you fit? · Tailor my résumé · Write a cover letter

Company
Altera
Where
Bengaluru, Karnataka, India
Level
Senior
First seen
October 21, 2026
Listed via
Workday

What the posting says

Job Description: We are seeking a Senior FPGA Soft IP Development Engineer to own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property (IP) blocks. In this role, you will be responsible for developing critical system-level IP cores—including advanced AMBA AXI Interconnect IP - ensuring their portability, scalability, and timing closure across diverse FPGA architectures. Responsibilities - Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and…

Read more and apply on Altera's site

This page includes information from the O*NET 31.0 Database by the U.S. Department of Labor, Employment and Training Administration (USDOL/ETA). Used under the CC BY 4.0 license. O*NET® is a trademark of USDOL/ETA.