Destava

IP Logic Design Engineer

Altera is hiring for IP Logic Design Engineer in Bengaluru, Karnataka, India. Mid level. First seen September 21, 2026; open as of November 11, 2026. Jobs taken straight from company career pages — no aggregator in between.

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Company
Altera
Where
Bengaluru, Karnataka, India
Level
Mid
First seen
September 21, 2026
Listed via
Workday

What the posting says

This role spans architecture, Verilog/SystemVerilog implementation, Quartus flows and timing closure, board bring-up, interface validation, and system-level debug. The ideal candidate can move comfortably from a system requirement or board schematic to a robust RTL implementation, then bring the design up on hardware and isolate issues across RTL, board, clocking, reset, memory, transceiver, and software boundaries. What you will do - Define FPGA architecture, microarchitecture, block diagrams, interface behavior, register maps, clocking, reset strategy, and implementation plans for…

Read more and apply on Altera's site

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