FPGA SW Validation Engineer (PR)
Altera is hiring for FPGA SW Validation Engineer (PR) in Bengaluru, Karnataka, India. Mid level. First seen November 12, 2026; open as of November 13, 2026. Jobs taken straight from company career pages — no aggregator in between.
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- Company
- Altera
- Where
- Bengaluru, Karnataka, India
- Level
- Mid
- First seen
- November 12, 2026
- Listed via
- Workday
What the posting says
Job Description: Job Description 1. Validates and researches the Compiler optimizations, Partial Reconfiguration (PR) flow, Debuging features like SignalTap & System Console, etc. using Quartus Design Software and Altera FPGA Hardware. 2. Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA Hardware Boards. 3. Regresses the designs during each release for QoR, and monitors performance over the targeted FPGA devkits to assess improvements. 4. Collaborates with cross-functional teams to develop and improve validation strategies for improving…
Read more and apply on Altera's site
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